The present invention relates to method for fabricating a semiconductor device that transfers design pattern to the principal surface of a semiconductor substrate by an exposure light that passes through a mask having the design pattern, and method for fabricating the semiconductor substrate used in the semiconductor device.
The down sizing of MOS-type (metal-oxide-semiconductor) semiconductor device in the recent years has resulted in a strong need for miniaturizing process that reduces the width of wiring. Specifically, the technique of forming a miniaturized resist pattern using photolithography is most important to the miniaturizing process. In forming of a miniaturized pattern, the improvement of resolution is generally attempted by reducing the wavelength of the exposure light and/or increasing the NA (numerical aperture) of the exposure lens. However, the reduction in the wavelength of the exposure light and the increase in the NA of the exposure lens decrease the depth of focus of the exposure light, and thus a sufficient depth of focus cannot be attained.
As a result, one of the important factors in the miniaturizing process resides in maintaining a uniform distance between the lens and the semiconductor substrate (wafer) of which surface is to be exposed to the exposure light, at each position above the wafer. The focal point of the exposure light can be adjusted by mechanically correcting the focal distance such as tilting the stepper stage with respect to the focal distance. However, such mechanism for correcting the focal distance can only be applied with respect to one shot of one exposure, and since the correction within the sort is not possible, the uniformity of focal distance within the shot becomes extremely crucial. Generally, the exposure region (site) of a shot has a dimension of 25 mm×25 mm in the stepper and 26 mm×8 mm in the scanner stepper.
The factors that determine the precision of the focus depend on the lens and the stage operation mechanism. In addition, the step resulted from the pattern formed on the principal surface of the wafer before exposure also affects the precision of the focus. Hence, a flat wafer of which principal surface having the smallest deviation from the virtual plane (an ideal exposure surface) and the smallest deviation with respect to the focal position is required. As a result, conventionally, a wafer of which flatness is being increased to a high level of substantially the same as the design rule is used to solve the problem of the decrease in depth of focus. Accordingly, the conventional flat wafer is basically a wafer having a small variation in thickness, and when a wafer having a small variation in thickness is held on a stepper stage, the deviation between the principal surface of the wafer and the focal plane becomes small and thus a high precision pattern can be formed.
However, after various investigations, the applicant of the present invention discovered that the deviation between the principal surface of the wafer and the focal plane does not merely depends on the uniformity of thickness of the wafer, but rather on how the principal surface of the wafer is positioned with respect to the optical system in the stepper when the wafer is held on the stepper stage. In other words, improving the uniformity of thickness of the wafer with which the exposure light does not come in contact may not achieve the miniaturizing process.
The problems between the conventional wafer and the stage holding the wafer are describe below with reference to the drawings.
FIGS. 14A to 14C schematically illustrate the case in which a conventional wafer having a high level of flatness and of which deviation of thickness is being kept to its smallest is held on a stage.
As shown in FIG. 14A, the film thickness of a wafer 100 is uniform and if the wafer 100 is an ideal wafer having no irregularity on the top and the underlying surfaces, no problem will occur. Moreover, if a stage 200 also has an ideal flatness, even if there are slight irregularities in the wafer, the irregularities can be flattened when the wafer is compressed onto the stage 200. Hence, values A, B, C, D of the deviation between the principal surface of the wafer 100 and the virtual focal plane 50 are equal.
However as shown in FIG. 14B, even though the values E, F, G, H of thickness measured at various points of the wafer 100 are equal, slight irregularities actually occurs on the conventional wafer 100 that is supposed to have a high level of flatness. Wafer on which irregularities occur such as the wafer 100 is known as snake wafer. Moreover, the conventional stage 200 also does not have an ideal flatness or a complete absorption.
FIG. 14C illustrates the conventional wafer 100 with irregularities being held on a pin chuck of the stepper stage 210. Accordingly, when the wafer 100 is compressed and held onto the pin chuck by vacuum absorption, the deviation may worsen depending on the condition of the underlying surface of the wafer 100. Hence, the most important concern in a photolithography process is to determine the flatness of the wafer 100 based not on the uniformity of the thickness of the wafer 100, but on the deviation of the thickness of the wafer from the virtual focal plane 50 when the wafer 100 is being held on the pin chuck of the stepper stage 210. The deviation not only depends on the condition and shape of the underlying surface of the wafer 100, but also greatly depends on the type and shape of the stepper stage 210.
Hence even if there is no thickness variation in the wafer 100, due to the relation between the shape of the underlying surface of the wafer 100 and the stepper stage 210, the top surface of the pin 211 and/or the seal portion 212, some of the pins 211 do not come in contact with the underlying surface of the wafer 100 and all the values A, B, C, D of the deviation with the virtual focal plane 50 are different. In other words, the principal surface of the wafer 100 held on the stepper stage 210 cannot be considered as flat.
Further, the flatness of the wafer 100 is conventionally determined by focusing on the uniformity of the thickness (variation of the thickness). The flatness is determined by measuring the thickness of the wafer by electrical method using capacitance or optical method using Fizeau interferometer under the condition in which the wafer 100 is in a free state and not being held on the stage. Moreover, the flatness of the principal surface of the wafer 100 is determined by absorbing and entirely leveling the underlying surface of the wafer 100 according to the chuck (stage) having an ideally flat surface. These measuring methods merely measure the thickness variation of the wafer 100, and the flatness determined from such thickness variation of the wafer 100 does not ensure the depth of focus during the actual exposure on the stepper.
Due to the foregoing reasons, it is very difficult to form a miniaturized and high precision lithography pattern on the conventional wafer 100 held on the wafer stage 210. In other words, by using the conventional methods that merely assume the uniformity in thickness of the wafer 100 implies the flatness of the wafer 100, fabrication of semiconductor device belonging to the generation having a design rule of 0.15 μm or less with high precision is extremely difficult.